Three families of patents, or patent applications, constitute the present IPR of the company. The original one (Dislocation and stress management by mask-less processes using substrate patterning and methods for device fabrication), with priority date April 26, 2011; a second one (Method for industrial manufacturing of a semiconductor structure with reduced bowing), with priority date April 27, 2016; and the most recent Italian patent application (Method for producing a freestanding and stress-free epitaxial layer starting from a disposable substrate patterned in etched pillars array), deposited on November 5, 2020.
Applications for strategy A:
Any material on any substrate, according to induced kinetic deposition process, with surface diffusion lengths shorter, or comparable to pillar width. Crystal quality much better than usual heteroepitaxial films, surface quality of vertical sidewalls much better than the ones produced by DRIE processes.
Actually, more interesting for devices with dense columnar arrays, like detectors (in particular, Single Photon Avalanche Detectors), photonic devices, vertical power devices with innovative parallel architecture.
Applications for strategy B:
Any material on any substrate. This technology is particularly good if isolated horizontal power devices (by 3C-SiC or GaN) are to be integrated in a Si wafer, so that a logic transistor can drive the performance of the power device. In such a case, a patch of 500-1000 µm, at much reduced bowing, can be produced, surrounded by one oxide/dielectric ring, to preserve the logic region from the detrimental elecric fields. The same strategy could be interesting for Si-integrated LEDs or sensors.
The 3C-SiC film (cubic, but oriented along the <111> direction) can also be used as a template for hexagonal GaN (integrated) deposition, either on still separated pillars (5-10 µm in width), or larger merged patches (500-1000 µm in width).
Applications for strategy C:
Any material on any substrate. This technology is particularly good if new, freestanding and relaxed substrates are to be produced, both for device manifacturing, and for subsequent heteroepitaxial deposition, including possible CMP process. Defect reduction with thickness can be exploited, with no issue related to bowing and cracks. 3C-SiC may be used, for instance, as a substrate for GaN deposition, at much reduced lattice misfit.
In terms of costs, patterning is apparently expensive, but as the masks and the process are optimized for the well known Si substrates, it could allow for cost reduction with respect to more expensive substrates, in terms of materials. The spontaneous liftoff does not require additional steps, but any mechanical procedure to favour/optimize the film liftoff has been included.