The three-dimensional growth of columnar and facetted crystals on top of the pillars is generated by a non-conformal epitaxy, as provided by a short diffusion length of the deposited species and the lateral shielding of the gaseous flow by a dense array of pillars. Tens of papers concerning Ge, GeSi, GaAs, and 3C-SiC on deeply patterned Si substrates have been published in the last ten years, concerning several beneficial effects of such compliant substrates: we group these effects into three strategies with different aims. 


Strategy A:

This technology, originally developed by Hans von Kaenel (ETH Zuerich and Politecnico of Milano) and Leonida Miglio (University of Milano-Bicocca), founders of the start-up company Pilegrowth Tech, is intended to doctor lattice-misfit defects and thermal-misfit wafer bowing with cracks in heteroepitaxy. The basic idea is to induce a vertical growth of any semiconductor on top of pillar arrays, by 1) depositing out of equilibrium conditions, so that the surface diffusion is minimized, and 2) designing a sufficently dense pillar array, so that the gaseous flux impinging on the lateral sidewalls is shielded by the neighbouring pillars. A fully vertical growth can be obtained, where columns of the deposited material are obtained, as tall as tens of microns and spaced by some 100-200 nanometers.

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In such conditions, extended defects,  such as threading arms of dislocations originating at the heteroepitaxial interface, are terminated at the sidewalls of the columns.  This strategy was first applied to Ge and SiGe on Si (001) and (111), as deposited by Low Energy Plasma Enhanced CVD, and to GaAs on Ge/Si and on Si (001), by Metal organic Vapour Phese Epitaxy and Molecular Beam Epitaxy. The top growth front can be tailored by growth conditions to obtain fully slanted facets that drive the dislocations out at the sidewalls.

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By suitable prolonged annealing, or changing the growth conditions, full merging of the top part of the columns can be obtained, providing a suspended continuous film on the pillars. See, for example, the case og Ge on Si (001).

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Strategy B:

A second target was to hinder the wafer bowing and the cracks generated by the thermal misfit in case of a suspended film, as produced by the merging of individual columns on pillars, or wafer-bonding a film on pillars at high temperature. This strategy was applied to Ge on Si (001) by LEPECVD and to 3C-SiC on Si(001) and (111) by a hot wall reactor of LPE SpA. The concepts here are that:

1)The elastic tilting of the patterned pillars doctor the different thermal retraction of the film with respect to the substrate, in the cooling process.

2)There is a quantitative relationship between the horizontal size of the continuous film, as arranged in patches of some/several hundreds µm, and the aspect ratio of the pillars, for a much reduced warping.

We first applied this strategy of “pillars in controlled arrays” to the case of Ge on Si(001):



Rotation of the pillars (mostly the peripheral ones):



Reduction of the thermal strain:


This strategy was used in the most difficult case of 3C-SiC on Si (111), where in planar substrates it is not possible to growth more than one micrometer SiC. Here L is the patch size and R is the curvature radius of the wafer, whereas the film thickness is of the order of 12-20 micrometers, with no cracks:




The experiments by CVD with one hot-wall reactor of LPE SpA demonstrated that the bowing was greately reduced and also the staking fault density, usually affecting any cubic SiC film can be reduced at the filling voids between hexagonal pillars:



The pillars can be carved even for a few tens of microns by a Deep Reactive Ion Etching process, and a nice SiC film in separated patches can be obtained up to 20-25 micrometers:


Strategy C:

If the aim is producing a thick (one hundred to some hundreds µm) freestanding layer, in order to reduce at minimum the defect density, and disposing the Si substrate, the pillar dimensions and shape can be engineered to provide a spontaneous lift-off, induced by the thermal stress. This strategy was preliminarly applied to 3C-SiC grown on Si(111) by a hot wall reactor of LPE SpA.

The main concepts, here, are:

1) The pillars are uniformely T-shaped, with a necking produced by a two-step etching process (vertical plus isotropic), so that the thermal stress in cooling breaks all the neckings.

2) The pillar array architecture provides a decoupling of the deposited layer on pillars from the film deposited on unpatterned areas, either by deep tranches, or by nitride/oxide masking, so that the layer is freed.



The deposited 3C-SiC film is here 80 micrometers, approximately, and the patches (as wide as 500 micrometers) are eventually fused in fast-growth conditions, so that a countinuous suspended film is obtained all across the wafer. In cooling down from 1370 °C to RT, all the pillars are brocken at the necking:


So that the film is released by the substrate, but for the peripheral perimeter of the wafer, where no pattering was performed, nor any discotinuity of the film was yet operated. The stress to the substrate is therefore still present from the pinned margins, so that the wafer is eventually broken:


The bottom part of the SiC film still shows the patches signature and incorporates all the tops of the T-shaped pillars


whereas the top part of the film is continuous and monocristalline, all across the wafer: